verilog中调用其他模块出现问题
想在顶层模块中调用下层模块，在顶层模块中写了include语句，可是出现module can not be declared more than once的错误，请问怎么解决？求高手指点。。。

[解决办法]
You don't have to use the include statement to include those submodules again.